New Architecture for EIA-709.1 Protocol Implementation

Abstract

This paper proposes a new architecture for EIA-709.1
protocol implementation. The protocol is conventionally
implemented with the proprietary processor and language,
Neuron chip and Neuron C, respectively, where the Neuron chip
consists of 3 processors inside. The proposed architecture uses
only one general purpose processor and general ANSI C to
implement the layers of EIA-709.1 except the physical layer. The
data link, network, and other layers are implemented onto one
RISC processor, ARM. Specifically, the data link layer of the
EIA-709.1 based on predictive p-persistent CSMA/CA is
implemented. The interface between the transceiver based on
power line communication and the data link layer based on the
ARM is described. As a conclusion, this research shows the
improvement of performance and the compatibility with the
existing Neuron chip.